With the increasing use of battery operated mobile electronic devices, VLSI circuit designers am continuously focusing on approaches to low power designs. We present an evolutionary cell placement technique for low power VLSI standard cell placement. The proposed technique is based on two evolutionary algorithms namely Tabu Search and Genetic Algorithm. Experiments were carried out using representative circuits from ISCAS85/89 benchmark suite. For the comparison purposes, we also implemented CA for our problem and compared placements results of the proposed technique to those of GA. The comparison shows that the proposed technique outperforms CA both in terms of quality of final placement solution obtained as well as CPU run time requiremen...
In this paper we present a timing -driven placer for standard-cell IC design. The placement algorith...
In this paper we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI. ...
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
We engineer a well-known optimization technique namely tabu search (TS) (Sait and Youssef, 1999) for...
Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement ...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
In this paper, we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
We engineer a well known optimization technique namely Tabu Search (TS) [1] for the performance and ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
In this paper we present a timing -driven placer for standard-cell IC design. The placement algorith...
In this paper we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI. ...
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
We engineer a well-known optimization technique namely tabu search (TS) (Sait and Youssef, 1999) for...
Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement ...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
In this paper, we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
We engineer a well known optimization technique namely Tabu Search (TS) [1] for the performance and ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
In this paper we present a timing -driven placer for standard-cell IC design. The placement algorith...
In this paper we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI. ...
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm...