Improving the Accuracy and Efficiency of Junction Capacitance Characterization: Strategies for Probing Configuration and Data Set Size

Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capaci-tances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Addition-ally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time main-taining a high model accuracy. Index Terms—Bipolar and BiCMOS processes, bipolar transis-tors, capacitance measurement, parameter estimation. NOMENCLATURE Propagation delay of a logic circuit. Forward transit time. Cutoff frequency. Base parasitic series resistance. Emitter parasitic series resistance. Collector parasitic series resistance. Load resistance of logic gate. Intrinsic base-collector junction capacitance. Extrinsic base-collector junction capacitance. Base-emitter junction capacitance. Collector-substrate junction capacitance. Base-emitter junction diffusion capacitance. Load capacitance of logic gate. Transconductance. I