Analysis of intrinsic and parasitic gate delay on InGaAs HEMTs. ECS Trans 2008;16:65–72

In this paper, the principles, measurement techniques, and analysis of the gate delay of high-electron-mobility-transistors (HEMTs) mainly based on an InP material system are discussed. In the measurement techniques, de-embedding of the pad parasitics is also described. The intrinsic part of the gate delay of HEMTs is the transit time for electrons to travel in the gate depletion region. When the gate length is large enough, the intrinsic gate delay is dominant in the total gate delay. However, as the gate length becomes less than 100 nm, the delay analysis reveals that the intrinsic gate delay is now no longer dominant but the parasitic gate delay ascribed to the resistance and capacitance out of the gate region. Based on these results, ways for further improvement of the frequency response are also discussed