* T)C FILE COPY On-chip Instruction Caches

D T IC " Ctimied ilcrees in clock rates of VLSI procsors demand a reduc-EL C Etion in the fi-quency of expesive off-chip memory references. With.EL C E out such a reducio, the chp croin time and the consrant of JUN 18 W, external logic will severely impact the clock cycle. y absorbing large fraetion of instruction references, on-chip caches substantially reduce f-chip communication. Minmiing the average instruction access time with a limited silicon budget requires careful analysis ofD both cache architecture and implementation. This paper examines some important design issues and tradeos that maximize the perfor-mance of on-chip instruction caches, while retaining implementation cse. Our discussion focuses oan the instruction cache design for MIPS-X. a pipelined, 32-bit, reduced instruction set, 20 MIPS peek, CMOS processor designed at Stanford. The on-chip instruction cache is 2K! m OrroN STAT E A bytes and allows single-cycle instruction accmses. Trace driven simu-| or pubi *e | i; lations show that the cache has an average miss rate of 12 % resulting • Droe fo public r. in an average instruction access time of 1.24 cycles. €,,'4-amtiblo Unlim~ited V.4S-