Towards Optimal Performance-area Trade-off in Adders by Synthesis of Parallel Prefix Structures

This paper proposes an efficient algorithm to synthesize pre-fix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph struc-tures to optimize an objective function such as size of pre-fix graph subject to constraints like bit-wise output logic level. Besides having the best performance-area trade-off our approach, unlike existing techniques, can (i) handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and (ii) generate several feasible solutions that minimize the objec-tive function. Generating several optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are dif-ficult to model as constraints during logic synthesis. Ex-perimental results demonstrate that our approach improves performance by 3 % and area by 9 % over even a 64-bit full custom designed adder implemented in an industrial high-performance design