DOI 10.1007/s11265-010-0477-6 A Flexible LDPC/Turbo Decoder Architecture

Abstract Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most power-ful error correcting codes that are widely used in mod-ern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be re-quired. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a uni-fied message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15 % area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized o