HHNEC 0.18um BCD Technology for high density power integration

is presented. This technology provides both N type and P type power LDMOS with capability of voltage up to 40V applications; these power LDMOS devices have competitive specific on-resistance; the parasitical miller capacitance and SOA of power LDMOS devices are optimized by careful device and layout design; it also provides HVCMOS with voltage up to 40V analog application; the bipolar devices in this technology are also optimized for power switching as standard bipolar process offers. The 1.8V/5.0V CMOS devices are performance compatible with industry main stream 1.8V/5.0V CMOS technology. This platform is modularized with various options; it can be separated int