, Ulrich Trunk

This paper details the development steps of the 128 channel pipelined readout chip Beetle, which is be-ing designed for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detec-tors 1 of LHCb. Section II. summarizes the Beetle chip architec-ture. Section III. shows the key measurements on the rst chip version (Beetle1.0) which drove the design changes for the Beetle1.1. First performance data of the new chip is presented in section IV., while an out-look on the future test and development of the chip are given in section V. I