Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

We present Synchroscalar, a tile-based architecture for embedded processing that is designed to provide the flex ibility of DSPs while approaching the power efficiency of ASICs. We achieve this goal by providing high parallelism and voltage scaling while minimizing control and commu nication costs. Specifically, Synchroscalar uses columns of processor tiles organized into statically-assigned frequency-voltage domains to minimize power consump tion. Furthermore, while columns use SIMD control to min imize overhead, data-dependent computations can be supported by extremely flexible statically-scheduled com munication between columns. We provide a detailed evaluation of Synchroscalar in cluding SPICE simulation, wire and device models, syn thesis of key components, cycle-level simulation, and compiler- and hand-optimized signal processing applica tions. We find that the goal of meeting, not exceeding, per formance targets with data-parallel applications leads to designs that depart significantly from our intuitions de rived from general-purpose microprocessor design. In particular, synchronous design and substantial global in terconnect are desirable in the low-frequency, low-power domain. This global interconnect supports parallelization and reduces processor idle time, which are critical to en ergy efficient implementations of high bandwidth signal processing. Overall, Synchroscalar provides programma bility while achieving power efficiencies within 8-30X of known ASIC implementations, which is 10-60X better than conventional DSPs. In addition, frequency-voltage scal ing in Synchroscalar provides between 3-32 % power sav ings in our application suite. 1