Effective Use of The Level-Two Cache for Skewed Tiling

Tiling is a well-known loop transformation technique to enhance temporal data locality. In our previous work, we have developed a skewed tiling technique for relaxation codes, which requires to apply loop skewing before loop tiling. In this paper, we study how to effectively usc the level-two cache for skewed tiling through a tile-size selection algorithm, STS. Particularly, we address two questions: (1) when to foclls on enhancing locality for the L2 cache instead of the Ll cache, and (2) how to improve the L2 cache locality such that the overall performance nm be improved. \Ve address the first question by developing an execution cost model which incorporates both the Ll and the L2 cach( ~ misses. \Ve address the second question by applying inter-array padding to minimize cross-interference misses. We compare STS with several previonsly known algorithms. For certain test cases, STS is significantly better than those previolls algorithms because it effectively exploits the L2 cache locality. For other cases, STS achieves comparable results because it also effectively exploits the Ll cache locality. For two well-known SPEC benchmarks with different inputs on two dif-ferent machines, we also compare our inter-array padding algorithm with a previously-proposed padding algorithm. Our padding algorithm is significantly bel.ter