Power Analysis for Deep Submicrometer Conventional MOS Transistors

(Received 2/2/2012; accepted for publication 17/4/2013) Abstract. Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For the dynamic power the voltage, capacitance and frequency are the major components of the power dissipation. In this paper, we propose a new power macromodeling technique for the power estimation of complementary metal-oxide- semiconductor (CMOS) inverter using 0.12µm technology. As the dynamic power is directly linked with the load capacitance (CL), it is also a lumped capacitance of all internal parasitic capacitances. In our model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for the power consumption of the CMOS inverter. The Preliminary results are effective and our macromodel provides the accurate power estimation