A 660-W 50-Mops 1-V DSP for a Hearing Aid Chip Set

Abstract—This article presents the flow and techniques used to design a low-power digital signal processor chip used in a hearing aid system implementing multiband compression in 20 bands, pat-tern recognition, adaptive filtering, and finescale noise cancella-tion. The pad limited 20 mm2 chip contains 1.3 M transistors and operates at 2.5 MHz under 1.05-V supply voltage. Under these con-ditions, the DSP consumes 660 W and performs 50 million 22-bit operations per second, therefore achieving 0.013 mW/Mops (milli-watts per million operations), which is a factor of seven better than prior results achieved in this field. The chip has been manufactured using a 0.25- m 5-metal 1-poly process with normal threshold volt-ages. This low-power application-specific integrated circuit (ASIC) relies on an automated algorithm to silicon flow, low-voltage oper-ation, massive clock gating, LP/LV libraries, and low-power-ori-ented architectural choices. Index Terms—Algorithm optimization, digital signal processing, gated clock techniques, low power design. I