Instruction-level simulation is necessary to evaluate new ar-chitectures. However, single-node simulation cannot predict the behavior of a parallel application on a supercomputer. We present a scalable simulator that couples a cycle-accurate node simulator with a supercomputer network model. Our simulator executes individual instances of IBM’s Mambo PowerPC simulator on hundreds of cores. We integrated a NIC emulator into Mambo and model the network instead of fully simulating it. This decouples the individual node simulators and makes our design scalable. Our simulator runs unmodified parallel message-passing applications on hundreds of nodes. We can change network and detailed node parameters, inject network traffic directly into caches, ...
Simulation is a popular approach for predicting the performance of MPI applications for platforms th...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
As multiprocessor systems-on-chip become a reality, perfor-mance modeling becomes a challenge. To qu...
Discrete event simulation is widely used within the networking community for purposes such as demon-...
Architecture simulation tools are extremely useful not only to predict the performance of future sys...
Parallel simulation techniques are promising for reducing the simulation time and for increasing the...
Chip-multiprocessor (CMP) architectures present a challenge for efficient simulation, combining the ...
In this paper we propose a methodology for the study of general cache networks, which is intrinsical...
This paper examines the cost/performance of simulating a hypothetical target parallel computer using...
Today, even the simplest laptop processor has at least four cores and a graphics card containing ten...
[[abstract]]In recent years, it has gradually become popular to use discrete-event simulation as a t...
speedup As the scale of parallel machine grows, communication network is playing more important role...
In this paper, we introduce a novel modeling tech- nique to reduce the time associated with cycle-ac...
Abstract—The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolki...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
Simulation is a popular approach for predicting the performance of MPI applications for platforms th...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
As multiprocessor systems-on-chip become a reality, perfor-mance modeling becomes a challenge. To qu...
Discrete event simulation is widely used within the networking community for purposes such as demon-...
Architecture simulation tools are extremely useful not only to predict the performance of future sys...
Parallel simulation techniques are promising for reducing the simulation time and for increasing the...
Chip-multiprocessor (CMP) architectures present a challenge for efficient simulation, combining the ...
In this paper we propose a methodology for the study of general cache networks, which is intrinsical...
This paper examines the cost/performance of simulating a hypothetical target parallel computer using...
Today, even the simplest laptop processor has at least four cores and a graphics card containing ten...
[[abstract]]In recent years, it has gradually become popular to use discrete-event simulation as a t...
speedup As the scale of parallel machine grows, communication network is playing more important role...
In this paper, we introduce a novel modeling tech- nique to reduce the time associated with cycle-ac...
Abstract—The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolki...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
Simulation is a popular approach for predicting the performance of MPI applications for platforms th...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
As multiprocessor systems-on-chip become a reality, perfor-mance modeling becomes a challenge. To qu...