3D-SWIFT: a High-performance 3D-stacked Wide IO DRAM∗

Wide IO has been standardized as a low-power, high-bandwidth DRAM for embedded system. The performance of Wide IO, how-ever, is limited by the power constraint and unexploited fine-grained memory parallelism. In this work, we propose a novel architecture, 3D-SWIFT, that achieves high access parallelism by partitioning a memory bank into sub-banks with a fine access granularity, which takes advantage of 3D die-stacking. The power constraint is nat-urally eliminated by the fine-grained structure due to the reduced activation power. Moreover, we propose sub-bank autonomy and introduce corresponding management policies to enable an intel-ligent interface protocol. Thanks to sub-rank autonomy, the over-head of tracking huge concurrent accesses in the memory controller is significantly reduced, making our 3D-SWIFT architecture scal-able for future memory systems. We evaluate our 3D-SWIFT and the results show that 3D-SWIFT can achieve 87.6 % performance improvement compared to the state-of-the-art Wide IO. 1