Analysis and Design of a DSP-based VLSI architecture for hearing aids

My dissertation consists in a feseability study for the realization of a SOC for hearing aids. The state of the art of the chips for those prosthesis consists in DSP-based architecures which have the main advantages of providing acceptable performances, being flexible toward innovations and programmable. The last advantage allows to progeam the hearing aids according to the user's needs. Firt of all, a state of the art analysis has been executed, which confirms these facts. After that, a requirements analysis has been executed, underlining both the functional requirements (necessity of compressing the input signal, reducing the environmental noise, etc.) and the project requirements (low-power oriented - desing, low - latency design architecture,etc.). After that, a simulation of the DSP algorithms have been performed using Simulink - Matlab, in order to understand what solutions lead to best results, allowing to start a preliminary desing of several subsystem of the chip. A preliminary architecture of several blocks has been implemented: the input interface, the output interface, harwdare accelerators for the studied algorithms, audio datapath. The preliminary architectures have been simulated and their performances in term of latency, distortion, etc. have been extracted. It constituted a real first phase of design of the single subsytems which allowed to extimate the complexity of the chips in term of logical - arithmetic blocks (adders, multipliers, multiplexers) and offers an interesting starting point for the real desing phase. The study has provided two outputs: a preliminary datasheet of the system and a development plan of the project