This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line tunneling parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation and a counter doped pocket within the SiGe layer at the source tunnel junction, resulting in a high on-current Ion = 6.7 μA/μm at a supply voltage VDD = -0.5 V and a constant subthreshold swing (SS) of about 80 mV/dec over four orders of magnitude of drain-current Id
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
Scaling of nanoelectronics consequently comes along with power consumption in integrated circuits, e...
Abstract This article presents a new line tunneling dominating metal–semiconductor contact-induced S...
This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS...
In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting re...
This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect...
In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFE...
Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade su...
Over the last 50 years, conventional scaling (Moore’s law) has provided continuous improvement in se...
Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunne...
This paper presents a new integration scheme to fabricate a Si/Si 0.55 Ge0.45 heterojunction line tu...
This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunne...
We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel ...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized f...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
Scaling of nanoelectronics consequently comes along with power consumption in integrated circuits, e...
Abstract This article presents a new line tunneling dominating metal–semiconductor contact-induced S...
This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS...
In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting re...
This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect...
In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFE...
Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade su...
Over the last 50 years, conventional scaling (Moore’s law) has provided continuous improvement in se...
Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunne...
This paper presents a new integration scheme to fabricate a Si/Si 0.55 Ge0.45 heterojunction line tu...
This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunne...
We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel ...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized f...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
Scaling of nanoelectronics consequently comes along with power consumption in integrated circuits, e...
Abstract This article presents a new line tunneling dominating metal–semiconductor contact-induced S...