Low-Latency Architecture for Order Book Building

Information technology forms an important part of the world and algorithmic trading has already become a common concept among traders. The High Frequency Trading (HFT) requires use of special hardware accelerators which are able to provide input response with sufficiently low latency. This master's thesis is focused on design and implementation of an architecture for order book building, which represents an essential part of HFT solutions targeted on financial exchanges. The goal is to use the FPGA technology to process information about an exchange's state with latency so low that the resulting solution is effectively usable in practice. The resulting architecture combines hardware and software in conjunction with fast lookup algorithms to achieve maximum performance without affecting the function or integrity of the order book