Interface Properties of Group-III-Element Deposited-Layers Integrated in High-Sensitivity Si Photodiodes

In this thesis, the research on silicon-based CMOS-compatible PureB technology was continued with the goal of enabling a PureB process module that could be added as a back-end module to wafers from a CMOS foundry. The properties of PureB layers deposited at low-temperature, particularly those deposited at 400°C were studied in more detail, among other things by introducing new electrical test structures. A new deposition method including gallium deposition, called PureGaB, was developed to alleviate some of the difficulties encountered when reducing the deposition temperature. Moreover, the capabilities of PureB technology were extended by a demonstration of highly-sensitive single-photon avalanche diodes (SPADs)