Exploiting Asynchrony In GPS Receiver Systems To Enable Ultra-Low-Power Operation

Many complex systems are inherently asynchronous. One simple example is the neural network in human bodies where neurons communicate with one another through synaptic signaling. They pass messages around efficiently without any dictation from a global timing reference. Another example is the GPS receiver system; though the satellite constellation is synchronized by atomic clocks, asynchrony is inherent in the operation of the receivers. Forcing some form of clocking to an asynchronous system will not only render it unnatural, but also makes it wasteful of resources. The same can be said about clocking an inherently asynchronous system using conventional VLSI techniques. This dissertation presents the concept and implementation of an asynchronous GPS baseband processor architecture designed for low power applications. All subsystems run at their natural frequencies without clocking and all signal processing is done on-the-fly. Transistorlevel simulations and measured power from system components in a 90nm process show that the system only consumes about 1.4mW during continuous tracking. The system also has 3-D rms error below 4 meters, comparing favorably to other contemporary GPS baseband processors