Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design

Integration of discrete charge storage in nanocrystals (NC) or dielectric traps is shown to alleviate limitations on tunnel oxide scaling and operational voltage reduction in conventional Flash memories. With the advantage of reduced voltages, NC-based memories become viable for integration in conventional SRAM cells to provide nonvolatile (NV) functionality. 10-transistor NV-SRAM cell was proposed and validated with SPICE-level simulations to provide useful guidelines into system level design of a nonvolatile microcontroller. However, discrete storage-based memory devices are known to increase variability in performance, restricting their progress towards full scale production. One method towards reducing variation investigates the effect of engineered nanopores in the tunnel oxide and charge-trap layer of Flash memory gate stack. Nanopores are shown to generate preferred tunneling paths for electron injection by field enhancement in the porous medium as well as render better retention characteristics to the memory at the expense of lower memory window. In order to propel Flash memory into the low-voltage and fast-programmable device regime, integration of ferroelectric (FE) thin film with discrete charge storage into a single hybrid memory device was proposed. Storage of gate-injected electrons adds to the memory window generated by ferroelectric polarization and reduces the depolarization field in the ferroelectric during retention. The first generation of these devices integrated ferroelectric PVDF polymer and HfO2 trap layer to demonstrate larger memory window and longer retention compared to conventional FE -FETs. The dynamics of ferroelectric switching in the hybrid gate stack naturally establishes a two-step program mechanism of faster polarization alignment followed by slower electron tunneling into the storage layer. This was ver ified by the fabrication of second generation of low-voltage hybrid devices with PZT thin film and Au NC. These devices demonstrated fast DRAM-like switching as well as slower Flash-like operation with distinct signatures from the two memory mechanisms in both program and retention dynamics. A statistical switching model describing ferroelectric switching was integrated in simulations for conventional Flash memory dynamics to corroborate the proposed dual-speed program mechanism in the hybrid device and provide realistic estimates of program and retention transients for the two distinct modes