Integration of Photodetectors and Optical Receiver

As computing systems and communication networks grow more complex, so is the need for higher bandwidth data links. Optical interconnect promises to offer lowercost, high-bandwidth data communication at a lower cost than electrical equivalents. This thesis investigates two different implementations of optical receiver frontend circuits with photodetectors to take advantage of the unique properties of inexpensive mature CMOS technologies. The first optical receiver integrates a SiGe phototransistor monolithically with the front-end circuits in a 0.18um BiCMOS technology. This technique enables monolithically integrated detector design and lowers manufacturing cost. It also enables detectors with smaller parasitic effects to help boost the receiver performance. With the phototransistor, we measured an receiver operation speed of 1 Gb/s. The second design implements a 10 Gb/s receiver in a 0.25um silicon-onsapphire technology with a flip-chip bonded commercial photodetector. We take advantage of the lower parasitic in devices and various circuit techniques to achieve the 10 Gb/s operation. This is the first reported 10 Gb/s optical receiver front-end with photodetector and limiting amplifiers implemented in a 0.25um technology. These receiver implementations demonstrate ways to take advantage of mature commercial technologies in designing optical receiver front-end circuits to achieve high-performance, low-cost optical links