Part 3: VerificationInternational audienceMemory safety plays a crucial role in concurrent hardware/software systems and must be guaranteed under all circumstances. Although there exist some approaches for complete verification that can cope with both hardware and software and their interplay, none of them supports pointers or memory. To overcome this problem, we present a novel approach for model checking memory-related properties of digital HW/SW systems designed in SystemC/TLM. The main idea is to formalize a clean subset of the SystemC memory model using Uppaal timed automata. Then, we embed this formal memory model into our previously proposed automatic transformation from SystemC/TLM to Uppaal timed automata. With that, we can fully a...
Model checking transactional memories (TMs) is difficult because of the unbounded number, length, an...
The formal verification of a real-time system requires either a proof theoretic or model theoretic ...
Perhaps the most difficult aspect of designing a shared memory multiprocessor is the hardware protoc...
Abstract—Many designs intermingle large memories with wide data paths and nontrivial control. Verify...
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole rang...
Abstract-State-of-the-art hardware model checkers and equivalence checkers rely upon a diversity of ...
During the past few years, a number of software tools for automated analysis of real-time systems ha...
With increasing design complexity, verification becomes a more and more important aspect of the desi...
Concurrent designs can be automatically verified by transforming them into an automata-based represe...
In the ever-developing world of technology, more and more situations arise where the life of many pe...
In the age of submicron technology a single chip may contain tens or even hundreds of millions trans...
technical reportWe offer a solution to the problem of verifying formal memory models of processors b...
International audienceAsynchronous circuits have key advantages in terms of low energy consumption, ...
In order to handle the increasing complexity of hardware / software designs, system level design met...
Software transactional memories (STM) are described in the literature with assumptions of sequential...
Model checking transactional memories (TMs) is difficult because of the unbounded number, length, an...
The formal verification of a real-time system requires either a proof theoretic or model theoretic ...
Perhaps the most difficult aspect of designing a shared memory multiprocessor is the hardware protoc...
Abstract—Many designs intermingle large memories with wide data paths and nontrivial control. Verify...
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole rang...
Abstract-State-of-the-art hardware model checkers and equivalence checkers rely upon a diversity of ...
During the past few years, a number of software tools for automated analysis of real-time systems ha...
With increasing design complexity, verification becomes a more and more important aspect of the desi...
Concurrent designs can be automatically verified by transforming them into an automata-based represe...
In the ever-developing world of technology, more and more situations arise where the life of many pe...
In the age of submicron technology a single chip may contain tens or even hundreds of millions trans...
technical reportWe offer a solution to the problem of verifying formal memory models of processors b...
International audienceAsynchronous circuits have key advantages in terms of low energy consumption, ...
In order to handle the increasing complexity of hardware / software designs, system level design met...
Software transactional memories (STM) are described in the literature with assumptions of sequential...
Model checking transactional memories (TMs) is difficult because of the unbounded number, length, an...
The formal verification of a real-time system requires either a proof theoretic or model theoretic ...
Perhaps the most difficult aspect of designing a shared memory multiprocessor is the hardware protoc...