Bit Error Rate Detection in High Energy Physics Experimentsimplemented on an FPGA

The front-end readout electronics of the Compact Muon Solenoid (CMS) Hadron Calorimeter(HCAL) detector is controlled remotely by a back-end control system due to high radiationand a strong magnetic field. The transmission of the digital communication between back-endand front-end is established over a 4.8 Gbps fiber optic channel. In order to ensure continuousoperation and to enable diagnosis of possible problems, the communication is required to bereliable, thus detection of errors is crucial for the control system. To this end, the present thesisdeals with the design and the implementation of a Bit Error Rate (BER) detection on the fieldprogrammable gate array (FPGA) of the next generation Front End Control (ngFEC) module.BER is well know as one of the basic measures of the performance of any digital communicationsystem [1]. The Bit Error Rate Test (BERT) scheme used in this thesis consists of two modules:a pattern generator and an error detection module.The performance of the BER technique in the communication between the front-end readoutand the back-end control system is evaluated using a generic N-bit PRBS generator and anerror detection module implementation in the VHDL programming language on the Kintex R-7 (XC7K420T) FPGA. The Xilinx ISE tool (software) is used to develop the implementation ofthe BERT and provides the functional and timing simulation of the VHDL models. The BERcount measurements are done via scripts built on a server. The BERT is employed in varioustest stands and at the CHARM irradiation beam test. The results are presented and discussedin the present thesis