The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were a...
This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generation...
Abstract–Graphics Processing Units specifically designed for High Performance Computing applications...
Electronic systems in space and terrestrial environments are subjected to a flow of particles of nat...
The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented...
IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE)IEEE Catalog Number: CFP1...
The present thesis aims at evaluating the SEE static and dynamic sensitivity of three different COTS...
International audienceThis work evaluates the SEE static and dynamic sensitivityof a single-chip man...
La présente thèse vise à évaluer la sensibilité statique et dynamique face aux SEE de trois disposit...
The large computing capacity, great flexibility, low power consumption, intrinsic redundancy and hig...
This paper provides an experimental study of the single-event upset (SEU) susceptibility against the...
With the development of silicon technologies, the minimum feature size of transistors has scaled dow...
This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generation...
Abstract–Graphics Processing Units specifically designed for High Performance Computing applications...
Electronic systems in space and terrestrial environments are subjected to a flow of particles of nat...
The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented...
IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE)IEEE Catalog Number: CFP1...
The present thesis aims at evaluating the SEE static and dynamic sensitivity of three different COTS...
International audienceThis work evaluates the SEE static and dynamic sensitivityof a single-chip man...
La présente thèse vise à évaluer la sensibilité statique et dynamique face aux SEE de trois disposit...
The large computing capacity, great flexibility, low power consumption, intrinsic redundancy and hig...
This paper provides an experimental study of the single-event upset (SEU) susceptibility against the...
With the development of silicon technologies, the minimum feature size of transistors has scaled dow...
This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generation...
Abstract–Graphics Processing Units specifically designed for High Performance Computing applications...
Electronic systems in space and terrestrial environments are subjected to a flow of particles of nat...