IC Tested Load Board - High Speed Signals Layout Analysis

[[abstract]]本論文將針對現行業界晶片(IC)設計產業之最後測試階段(Final Test/FT)，做為IC與自動測試設備(Automatic Test Equipment)之間的傳輸媒介：IC測試載板(Load Board)，其高速訊號之佈局進行分析，以確保訊號在經由IC傳遞，透過腳座(Socket)及測試載板上的應用電路，乃至機台接收進行下，仍可維持其訊號完整性(Signal Integrity)。由模擬結果得知，本佈局分析在高板厚 > 3 2 mm、高層數 > 30 Layers、高速度8G bps、小孔徑6 mils、小間距0 4 mm之嚴峻條件下，仍能維持其訊號完整性，S參數在頻率8G Hz條件下，其射入損失(Insertion loss)可維持-3 dB以上，反射損失(Return loss)可抑制在-20 dB以下，特性阻抗(Characteristic Impedance)在傳輸線路徑上，其阻抗值皆可維持在+/-10%，眼圖(Eye Map)的振幅(Amplitude)高度能有效打開，抖動(Jitter)可有效地抑制，符合訊號規格。因此，透過本論文研究之設計工法，可確保測試載板之品質，以達到現行業界測試端之需求，以增加晶片產品的測試良率，進而提高產業競爭能力。[[abstract]]This paper focuses on the Final Test/FT stage of the current IC design industry IC tested Load Board is a transmitted interface board between IC and Automatic Test Equipment (ATE) The layout of high-speed signals are analyzed to ensure that the signals transmitted from IC through the socket and the application circuits on the load board can still maintain their signal integrity after the ATE receives them From the simulation results it can be seen that under severe conditions of high thickness > 3 2 mm high number of layers > 30 Layers high-speed of 8G bps small via holes size of 6 mils and fine pitch of 0 4 mm the layout analysis can still maintain its signal integrity The S-Parameter reaches a frequency of 8GHz the insertion loss can be maintained above -3 dB and the return loss can be suppressed under -20 dB The characteristic impedance value of the layout transmission line can be maintained within +/- 10% the amplitude value of the Eye Map can be effectively opened and jitter can be effectively suppressed that to meet the signals specifications Therefore through the design engineering methods used in this research the high-speed signals quality of IC tested load board can be ensured to meet the needs of the test-end of the existing industry standards Moreover the testing yield of IC products can be increased to further improve the industrial competitivenes