Investigations of MGy ionizing dose effects induced in thin oxides of micro-electronic devices

Total ionizing dose (TID) effects are studied for a long time in micro-electronic components designed to operate in natural and artificial environments. In most cases, TID induces both charge trapping in the bulk of irradiated oxides and the buildup of interface traps located at semiconductor/dielectric interfaces. Such effects result from basic mechanisms driven by both the shape of the electric field which stands into the oxide and of its fabrication process parameters which define pre-existing traps in the oxide’s bulk. From the pioneering studies based on “thick” oxides technologies to the most recent ones dedicated to innovative technologies, most of them concluded that the impact of total ionizing dose effects reduces with thinning the oxides. This is specifically the case for the gate-oxide of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) for which it is generally considered that TID is not anymore a major issue at kGy dose ranges. TID effects are now mainly due to charge trapping in the field oxides such as Shallow Trench Isolation. This leads to create either parasitic conduction paths or to Radiation-Induced Narrow Channel Effects (RINCE). Static current-voltage (I-V) electrical characteristics are then modified through a significant increase of the off-current of NMOS transistors or by shifting the whole I-V curves (of both NMOS and PMOS transistors) respectively. Based on these assumptions, no significant shift of I-V curves should be observed in modern bulk CMOS technologies. However, this paper presents evidences of large threshold voltage shifts measured at MGy dose levels despite the fact that transistors are designed in a submicron bulk technology which features a 7-nm thin gate-oxide. These electrical shifts are encountered on PMOS transistors of different widths, WNARROW = 0.24 μm and WWIDE = 10 μm. The devices are irradiated using 10 keV X-rays at several total dose steps up to 3 MGy. On the one hand, negative threshold voltage shifts of more than 3.3 V are extracted after 3 MGy on narrow transistors. Even very high, this voltage shift is consistent with RINCE in narrow open layout transistors. On the other hand, voltage shifts greater than 2.5 V are extracted on wide transistors. Obviously, this result should not be associated neither to positive charge trapping in the thin gate oxide nor to any RINCE in this very wide transistor geometry. The final paper will thus provide an extensive study of this effect using other device designs and geometries tested with dedicated TID experiments to discuss whether or not this effect revealed at very high TID, i.e. several MGy, may be attributed to an enhanced high-TID induced charge trapping mechanism in thin gate oxides