This thesis illustrates the usefulness of the full adder as the elementary cell for designing cellular arrays for arithmetic. It Is shown that basic arithmetic operations, number system conversion, matrix operations and computation of common library functions can be implemented using full adder arrays. It is further shown that fault detection is particularly easy in full adder arrays. The four neighbor full adder array can be tested for the presence of a single faulty cell by applying exactly eight tests, irrespective of the size of the array. The full adder arrays for practical applications turn out to be a little more difficult for fault detection. The number of tests is shown to grow almost linearly with the number of primary input termi...
The use of cellular automata has long been identified as a method, and means of modelling different ...
[[abstract]]The authors extend the Shen-Ferguson approach (1984) of testing carry-save (CS) array mu...
This work presents systolic architectures for implementing finite rings and fields operations in VLS...
Graduation date: 1979With the advent of LSI, iterative forms of realization\ud of digital systems ar...
Based on cell fault model, the paper studies test pattern generation and self test of tree adder, wh...
Systematic procedures to detect, locate and diagnose all single-cell failures in rectangular iterati...
[[abstract]]Design-for-testability techniques and built-in self-test structures are presented for ce...
In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmab...
Abstract. The general capabilities of fault tolerant computations in one-way and two-way linear cell...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
AbstractIn the complex computing system, processing units are dealing with devices of smaller size, ...
In the complex computing system, processing units are dealing with devices of smaller size, which ar...
Improved difficulty of the circuit tends to decline the reliability drastically and improved tendenc...
A programmable cellular array is investigated in this thesis. Each cell in the array is a multi-stat...
113 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The test methods of general i...
The use of cellular automata has long been identified as a method, and means of modelling different ...
[[abstract]]The authors extend the Shen-Ferguson approach (1984) of testing carry-save (CS) array mu...
This work presents systolic architectures for implementing finite rings and fields operations in VLS...
Graduation date: 1979With the advent of LSI, iterative forms of realization\ud of digital systems ar...
Based on cell fault model, the paper studies test pattern generation and self test of tree adder, wh...
Systematic procedures to detect, locate and diagnose all single-cell failures in rectangular iterati...
[[abstract]]Design-for-testability techniques and built-in self-test structures are presented for ce...
In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmab...
Abstract. The general capabilities of fault tolerant computations in one-way and two-way linear cell...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
AbstractIn the complex computing system, processing units are dealing with devices of smaller size, ...
In the complex computing system, processing units are dealing with devices of smaller size, which ar...
Improved difficulty of the circuit tends to decline the reliability drastically and improved tendenc...
A programmable cellular array is investigated in this thesis. Each cell in the array is a multi-stat...
113 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The test methods of general i...
The use of cellular automata has long been identified as a method, and means of modelling different ...
[[abstract]]The authors extend the Shen-Ferguson approach (1984) of testing carry-save (CS) array mu...
This work presents systolic architectures for implementing finite rings and fields operations in VLS...