Hardware-oriented parallel deadlock detection algorithms with reduced run-time complexity

Many modern embedded applications perform complex data processing. In recent years, Multiprocessor System-on-Chips (MPSoCs) have emerged to support these embedded applications. An MPSoC combines multiple embedded processors, specialized digital logic, and often mixed-signal circuits to provide a complete solution for embedded applications. In such an environment, the possibility that a system enters a deadlock state is greatly increased. Thus, resolving deadlock for MPSoCs in a timely and deterministic manner is critical for many embedded applications. To meet such possible demand for fast and deterministic deadlock detection mechanisms, this dissertation presents five parallel deadlock detection algorithms with reduced run-time complexities in hardware, which can be integrated into a variety of MPSoCs, targeting at a wide range of applications. The five hardware-oriented deadlock detection algorithms are: (i) Single-unit resource Deadlock Detection Algorithm (SDDA); (ii) Multi-unit resource Deadlock Detection Algorithm (MDDA); (iii) O(1) Single-unit resource Deadlock Detection Algorithm (OSDDA); (iv) Logarithmic Multi-unit resource Deadlock Detection Algorithm (LMDDA); and (v) Instant Multi-unit resource Deadlock Detection Algorithm (IMDDA). SDDA and OSDDA are only applicable for single-unit resource systems while MDDA, LMDDA, and IMDDA are applicable for both single-unit as well as multi-unit resource systems. All the proposed algorithms are devised based on a Resource Allocation Graph (RAG) representation of resource allocation status in the system. To implement the algorithms in hardware and thus exploit parallelism, the RAG is represented in adjacency matrices, which are implemented in hardware. Moreover, all five algorithms adopt a two-phase deadlock detection paradigm, which consists of a detection preparation phase and a deadlock detection phase. In the preparation phase, each proposed algorithm employs a unique technique to search for the reachable sink node of every resource. Then, all proposed algorithms use such information to perform O(1) deadlock detection. Briefly speaking, in its preparation phase, SDDA traverses all paths starting from every resource in parallel to search for the reachable sink node of each resource, which takes O(min(m,n)) run-time, where m is the number of processes and n is the number of resources. MDDA leverages a graph traversing technique with two levels of parallelism in its preparation phase, which also takes O(min(m,n)) run-time. OSDDA utilizes its classification of all resource allocation scenarios and performs only necessary operations to update resource allocation information. As a result, OSDDA has O(1) preparation. Inheriting the classification approach of resource events from OSDDA and combining it with exponential parallel graph traversing using a node hopping mechanism, LMDDA\u27s preparation phase takes O(log2(min(m,n))) run-time. IMDDA does not require any matrix computations to perform its preparation. Instead, it actualizes the RAG using a combinational digital circuit. Finding reachable sink nodes in the RAG is done by transmitting and combining special digital signals, called tokens, in the circuit. IMDDA preparation latency is thus only determined by gate delays in such a circuit. Lastly, a multi-threaded program written in Pthread and assisted by the proposed algorithms to detect and resolve deadlock during its execution, which represents a likely type of workload running on MPSoCs, is simulated using the Simics full-system simulator. Through simulation, the impact of the proposed hardware-based algorithms on the performance of the multi-threaded program is studied. Simulation results suggest that a faster deadlock detection algorithm incurs less resource allocation overhead in the execution of multi-threaded applications and thus can improve the overall application performance. Therefore, fast and deterministic deadlock detection algorithms can be very beneficial to time-critical applications running on MPSoCs