A medium-grain reconfigurable architecture for digital signal processing

A high performance low power mesochronous pipeline architecture for computer systems

Tatapudi, Suryanarayana Bhimeshwara, 1979-

January 2006

Thesis (Ph.D.), School of Electrical Engineering and Computer Science, Washington State Universit

Coarse grained reconfigurable architectures in the past 25 years: overview and classification

Wijtvliet, M.
Waeijen, L.
Corporaal, H.

January 2017

Reconfigurable architectures become more popular now general purpose compute performance does not in...

DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE

Joshua R. Templin
Joshua R. Templin

January 2010

This Thesis is brought to you for free and open access by the Graduate Studies a

Reconfigurable architectures for general-purpose computing

DeHon, André

January 1996

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...

Coarse-grain reconfigurable computing

Mirsky, Ethan A. (Ethan Avram)

January 1996

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...

Reconfigurable computing for radar front-end digital signal processing

Moeller, Tyler J. (Tyler John), 1975-

January 1999

Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and...

A fault-tolerant multiprocessor architecture for digital signal processing applications

Song, William S

January 1989

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...

Architecture syntesis for application-specific medium-throughput digital signal-processing chips

Vanhoof, Jan
Louvain, Katholieke Univ., Heverlee (Belgium). Departement Elektrotechniek

January 1992

SIGLEKULeuven Campusbibliotheek Exacte Wetenschappen / UCL - Université Catholique de LouvainBEBelgi...

Mapping of DSP Algorithms on the Montium Architecture

Heysters, P.M.
Smit, Gerardus Johannes Maria

April 2003

In battery operated mobile devices there is a growing need for flexible high-performance architectur...

A coarse-grained dynamically reconfigurable architecture for digital signal processing

Zhang, Chenxin
Thomas, Lenart
Henrik, Svensson
Öwall, Viktor

January 2009

This paper presents design and implementation of a coarse-grained reconfigurable architecture, targe...

Digital signal processing platform based on a novel dynamically reconfigurable array

Aslam, Nazish

January 2009

Dynamically reconfigurable processors are attracting significant interest in the semiconductor indus...

An environment for the development of digital signal processing software

Hebel, Kurt Joseph

January 10000

Prior to about 1980, real-time signal processing development work was dominated by hardware design t...

Reconfigurable signal processing and hardware architecture for broadband wireless communications

Liang, Y.-C.
Naveen, S.
Pilakkat, S.K.
Marath, A.K.

August 2005

10.1155/WCN.2005.323Eurasip Journal on Wireless Communications and Networking20053323-33

Compiling for coarse-grain reconfigurable architectures

Matsa, M. Morris E. (Moshe Morris Emanuel)

January 1997

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...

Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Zhang, Chenxin
Lenart, Thomas
Svensson, Henrik
Öwall, Viktor

January 2009

This paper presents the design and implementation of a coarse-grained reconfigurable architecture, t...

A high performance low power mesochronous pipeline architecture for computer systems

Tatapudi, Suryanarayana Bhimeshwara, 1979-

January 2006

Thesis (Ph.D.), School of Electrical Engineering and Computer Science, Washington State Universit

Coarse grained reconfigurable architectures in the past 25 years: overview and classification

Wijtvliet, M.
Waeijen, L.
Corporaal, H.

January 2017

Reconfigurable architectures become more popular now general purpose compute performance does not in...

DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE

Joshua R. Templin
Joshua R. Templin

January 2010

This Thesis is brought to you for free and open access by the Graduate Studies a

Reconfigurable architectures for general-purpose computing

DeHon, André

January 1996

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...

Coarse-grain reconfigurable computing

Mirsky, Ethan A. (Ethan Avram)

January 1996

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...

Reconfigurable computing for radar front-end digital signal processing

Moeller, Tyler J. (Tyler John), 1975-

January 1999

Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and...

A fault-tolerant multiprocessor architecture for digital signal processing applications

Song, William S

January 1989

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...

Architecture syntesis for application-specific medium-throughput digital signal-processing chips

Vanhoof, Jan
Louvain, Katholieke Univ., Heverlee (Belgium). Departement Elektrotechniek

January 1992

SIGLEKULeuven Campusbibliotheek Exacte Wetenschappen / UCL - Université Catholique de LouvainBEBelgi...

Mapping of DSP Algorithms on the Montium Architecture

Heysters, P.M.
Smit, Gerardus Johannes Maria

April 2003

In battery operated mobile devices there is a growing need for flexible high-performance architectur...

A coarse-grained dynamically reconfigurable architecture for digital signal processing

Zhang, Chenxin
Thomas, Lenart
Henrik, Svensson
Öwall, Viktor

January 2009

This paper presents design and implementation of a coarse-grained reconfigurable architecture, targe...

Digital signal processing platform based on a novel dynamically reconfigurable array

Aslam, Nazish

January 2009

Dynamically reconfigurable processors are attracting significant interest in the semiconductor indus...

An environment for the development of digital signal processing software

Hebel, Kurt Joseph

January 10000

Prior to about 1980, real-time signal processing development work was dominated by hardware design t...

Reconfigurable signal processing and hardware architecture for broadband wireless communications

Liang, Y.-C.
Naveen, S.
Pilakkat, S.K.
Marath, A.K.

August 2005

10.1155/WCN.2005.323Eurasip Journal on Wireless Communications and Networking20053323-33

Compiling for coarse-grain reconfigurable architectures

Matsa, M. Morris E. (Moshe Morris Emanuel)

January 1997

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...

Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Zhang, Chenxin
Lenart, Thomas
Svensson, Henrik
Öwall, Viktor

January 2009

This paper presents the design and implementation of a coarse-grained reconfigurable architecture, t...

A high performance low power mesochronous pipeline architecture for computer systems

Tatapudi, Suryanarayana Bhimeshwara, 1979-

January 2006

Thesis (Ph.D.), School of Electrical Engineering and Computer Science, Washington State Universit

Coarse grained reconfigurable architectures in the past 25 years: overview and classification

Wijtvliet, M.
Waeijen, L.
Corporaal, H.

January 2017

Reconfigurable architectures become more popular now general purpose compute performance does not in...

DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE

Joshua R. Templin
Joshua R. Templin

January 2010

This Thesis is brought to you for free and open access by the Graduate Studies a

A medium-grain reconfigurable architecture for digital signal processing

Abstract

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A medium-grain reconfigurable architecture for digital signal processing

Abstract

Extracted data

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