Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays

Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its small cell size, voltage and process compatibility with CMOS and nano-second read/write speeds. It exhibits high density (3-4x of SRAM), non-volatility and process scalability and hence is widely being considered as a viable alternative for SRAM in last-level caches. As the design and fabrication process matures for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models in STT-MRAM under both parametric variations as well as resistive defects (opens and shorts). Sensitivity of read, write and retention to process parameter variations such as lithographic and material variations are studied. In addition, defects (both intra-cell and inter-cell) and the corresponding fault models have been studied and data patterns which excite these faults are explored.M.S