Connect on the fly: enhancing and prototyping of cycle-reconfigurable modules

This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs , dynamic caches , and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. The integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. Applications for large- scale sorting, sparse matrix-vector multiplication, and Mem- cached are developed. The proposed modules enable 1.4 and 11 times reductions in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs