Macromodeling of I/O Buffers via Compressed Tensor Representations and Rational Approximations

This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulation