Nano Magnetic Logic: Modeling, Architectural Explorations and Simulation Tools

CMOS scaling is coming to an end due to limitations such as the increasing leakage current and minimum fabrication sizes achievable. Emerging technologies, that could replace CMOS in next years, are currently under investigation. These technologies will be able to process data at an extremely high operating frequency or with a remarkable reduction of consumed power. The ITRS report summarizes several possible technology solutions, among which carbon nano-tubes and graphene based devices, Quantum-dot Cellular Automata (QCA) and silicon nanowire based nanoarrays. Among these candidates, in this manuscript, the attention is focused on Quantum-dot Cellular Automata, and in particular to the Nano Magnetic Logic(NML) implementation since different studies envisage this technology as a promising alternative to CMOS. The Nano Magnetic Logic working principle is based on the interaction of field-coupled nanomagnets with typical dimension of 60nmx90nm or 50nmx100nm. Information are propagated through chains of these elementary devices according to their ferromagnetic and antiferromagnetic interactions. With this technology, binary information can be encoded in the magnetization verse, indeed, thanks to their very small dimension only two stable states can be recognized: Logic 1 are stored with an up magnetization, while Logic 0 are stored with a down magnetization. The main characteristic of NML are: I) the non-volatility of stored information; II) it is immune to radiation noise and high-energy alpha particles; III) it is an interconnection-free technology; IV) there is the possibility to store logic functions and memory onto the same device and V) it can be easily integrated with CMOS technology. In order to study this technology CAD Tools are needed; this can be useful for architectural explorations and to have terms of comparison with traditional CMOS. The ToPoliNano CAD Tool presented in this manuscript represents the answer to these points, it is able to automatically generate and simulate layouts based on NML starting from and architectural VHDL description. In this scenario, the software implementation of a VHDL parser for the internal representation of circuits represent a key point which makes possible to perform all the operations and the optimizations needed to elaborate the final layout. Another important feature of this instrument is the possibility to verify the correctness of the logical behavior of an NML circuit, for this reason an ad-hoc simulation engine has been developed and validated through a huge number of benchmarks. Thanks to ToPoliNano a thorough study on NML architecture has been made. The main features of ToPoliNano are: I) It is flexible and able to handle different emerging technologies; II) It exploits the same top-down approach of CMOS Tools; III) It is able to generate automatically generate layouts; IV) It allows to verify the correctness of logical NML-based circuits thanks to its specifically tailored simulation engines; V) Since the NML technology is not yet settled we need new techniques to take into account faults derived from the manufacturing process. This thesis focuses therefore on NML logic keeping into account these technology presents also some limitations that can be overcome introducing two other NML implementation: Magneto Tunnel Junctions (MTJ) and perpendicular-NML (pNML) as possible alternative to the traditional in-plane NML (iNML) implementation. Indeed, generally, in iNML circuits, the external fields are made through the use of wires carrying current and placed below the magnetic circuits. This principle has as main drawback, in addition of having high consumption in terms of power, not to allow access to the single cell; in other words, it is not possible to write a particular logical value of a single magnet. This limitation has been overcome by MTJ since cells can be driven through three control signals. In fact, the MJT are often used in combination with t