In this paper, we develop a specification methodology that documents and specifies a cache coherence protocol in eight tables: the states, events, actions, and transitions of the cache and memory controllers. We then use this methodology to specify a detailed, modern three-state broadcast snooping protocol with an unordered data network and an ordered address network that allows arbitrary skew. We also present a detailed specification of a new protocol called Multicast Snooping [6] and, in doing so, we better illustrate the utility of the table-based specification methodology. Finally, we demonstrate a technique for verification of the Multicast Snooping protocol, through the sketch of a manual proof that the specification satisfies a seque...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor design...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright...
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to v...
Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to ac...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
The coherence protocol is a first-order design concern in multicore designs. Directory protocols are...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Many future shared-memory multiprocessor servers will both target commercial workloads and use highl...
Disclosed herein is a cache coherence protocol for a distributed cache and a distributed strongly-co...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor design...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright...
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to v...
Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to ac...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
The coherence protocol is a first-order design concern in multicore designs. Directory protocols are...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Many future shared-memory multiprocessor servers will both target commercial workloads and use highl...
Disclosed herein is a cache coherence protocol for a distributed cache and a distributed strongly-co...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor design...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...