Background calibration of pipelined analog to digital converters

This thesis presents a novel adaptive self-calibration scheme that can correct linear static errors in a pipelined Analog-to-Digital Converters (ADCs). The technique is suitable for continuous background implementation. The proposed scheme consists of adapatively estimating residue correction parameters for each pipeline stage using a Least-Mean-Squares (LMS) algorithm. Foreground and Background digital and mixed-signal implementations of the proposed scheme have been shown to correct for capacitor ratio mismatch and finite amplifier gain errors in a pipeline stage. Formal mathematical treatment and simulation results are also presented to verify the efficiency of the scheme. A valuable modification to the adaptive LMS algorithm that greatly simplifies the background implementation of the calibration scheme has been proposed. It is termed Selective LMS algorithm. It proposes a use of single, offset-canceled comparator or another locally high resolution ADC for parameter estimation towards the calibration of the converter. At circuit level, a novel sampling network with improved spurious free dynamic range (SFDR) is proposed that involves bootstrapping both the gate and bulk during sampling. A prototype implementation in a TSMC 0.35μm is designed that includes all of the above novel ideas