University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: Sachin S. Sapatnekar. 1 computer file (PDF); ix, 104 pages, appendices A-C.Power grid design and analysis is a critical part of modern VLSI chip design and demands tools for accurate modeling and efficient analysis. In this thesis, we develop new solutions for solving power grids, both incrementally and in total, based on an approach that uses random walks. The process of power grid design is inherently iterative, during which numerous small changes are made to an initial design, either to enhance the design or to fix design constraint violations. Due to the large sizes of power grids in modern chips, updating the solution for these perturbati...
As the technology scales into 90nm and below, process-induced variations become more pronounced. In ...
Abstract—This paper proposes a novel stochastic method for analyzing the voltage drop variations of ...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
Power grid design and analysis is a critical part of modern VLSI chip design and demands tools for a...
This paper presents a linear-time algorithm for the DC analysis of a power grid, based on a random w...
It is found that the efficiency of the generic random walk analyzer varies for power grids with diff...
The purpose of this thesis is to expand the rigor of the development of new power flow solvers throu...
In this paper, we present a novel stochastic simulation approach based on extended Krylov subspace m...
Abstract—This article summarizes the basic concept of random walk algorithm. Random walk algorithm’s...
The classical method of solving random walk problems involves using Markov chain theory. When the pa...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.We propose a novel approach t...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
In this paper, we investigate the impact of interconnect and de-vice process variations on voltage f...
Random walks is one of the most popular ideas in computer science. A critical assumption in random w...
Power networks supply power from the P/G pads on a chip to the circuit modules. With the rapid incre...
As the technology scales into 90nm and below, process-induced variations become more pronounced. In ...
Abstract—This paper proposes a novel stochastic method for analyzing the voltage drop variations of ...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
Power grid design and analysis is a critical part of modern VLSI chip design and demands tools for a...
This paper presents a linear-time algorithm for the DC analysis of a power grid, based on a random w...
It is found that the efficiency of the generic random walk analyzer varies for power grids with diff...
The purpose of this thesis is to expand the rigor of the development of new power flow solvers throu...
In this paper, we present a novel stochastic simulation approach based on extended Krylov subspace m...
Abstract—This article summarizes the basic concept of random walk algorithm. Random walk algorithm’s...
The classical method of solving random walk problems involves using Markov chain theory. When the pa...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.We propose a novel approach t...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
In this paper, we investigate the impact of interconnect and de-vice process variations on voltage f...
Random walks is one of the most popular ideas in computer science. A critical assumption in random w...
Power networks supply power from the P/G pads on a chip to the circuit modules. With the rapid incre...
As the technology scales into 90nm and below, process-induced variations become more pronounced. In ...
Abstract—This paper proposes a novel stochastic method for analyzing the voltage drop variations of ...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...