Power management in multicore processors through clustered DVFS.

University of Minnesota M.S. thesis. July 2010. Major: Electrical Engineering. Advisor: Sachin Suresh Sapatnekar. 1 computer file (PDF); viii, 57 pages. Ill. (some col.)The need for high speed processors in recent years has increased the need to exploit more parallelism than instruction level parallelism (ILP) and thread level parallelism (TLP). As a result, chip multiprocessors have emerged as a solution for the high speed computing demands. Though a high throughput is achieved, power dissipation in chip multiprocessors is still a problem that needs to be addressed. A number of techniques for reducing both the active and static components of power exist. Dynamic voltage and frequency scaling (DVFS) is one of the schemes to reduce active power. DVFS is easy to implement for a single processor but if it has to be implemented for each core of a chip multiprocessor, a number of voltage regulators are required on chip and the area and power overheads associated with them surpass the advantages of having per-core control. On the other hand, one DVFS control for all cores cannot fully harness the potential for power reduction in each core. In this thesis, we look at the possibility of clustering the cores of a multicore processor and implementing DVFS on a per-cluster basis. We propose a scheme to find similarity among the cores and cluster the cores based on the similarity. We also provide an algorithm to implement DVFS for the clusters. We evaluate the effectiveness of per-cluster DVFS in power reduction by considering different number of clusters and different use cases for the applications running on the cores