An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

In this paper, we present a network interface (NI) for an on-chip network. Our NI decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP, and DTL. Our NI has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via NI ports using the network itself, instead of a separate control interconnect. An example instance of this NI with four ports has an area of 0.25 mm\u3csup\u3e2\u3c/sup\u3e after layout in 0. 13-µm technology, and runs at 500 MHz. U7 - Cited By (since 1996): 50 U7 - Export Date: 5 February 2010 U7 - Source: Scopu