A 50 – 60 GHz rectifier with −7dBm sensitivity for 1 V DC output voltage and 8% efficiency in 65-nm CMOS

This paper presents a 50 - 60 GHz fully integrated 3-stage rectifier in 65nm CMOS technology. The sensitivity of the rectifier is the limiting factor for an on-chip wireless-powered receiver in CMOS technology. In this paper, the technique of body-drain connection is proposed and implemented. In this method, the parasitic diode is shorted and the threshold voltage of the MOSFET is modulated, improving the sensitivity. Compared to the inductor peaking method [1] and other mm-wave rectifiers [2][3] in CMOS technology, the circuit proposed in this paper achieves high sensitivity and efficiency while maintaining a compact size, because no inductors are used inside the rectifier. The work achieves the peak sensitivity at 52 GHz, providing a 1-V dc output voltage for an input power of -7 dBm. The overall sensitivity over the entire operational range of 50 - 60 GHz is below - 2 dBm