A power-optimized high-speed and hig-resolution pipeline ADC with a parallel sampling first stage for broadband multi-carrier systems

This chapter analyzes the statistical properties of multi-carrier signals and their impact on ADC design, reviews the general pipeline ADC architecture and conventional low power design techniques, and presents a parallel sampling technique for pipeline ADC to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With the proposed parallel sampling technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence the overall signal to noise and clipping distortion ratio is improved. This technique allows reducing power dissipation and area in comparison to conventional solutions for converting multi-carrier signals. As an example, an 11b switched-capacitor pipeline ADC with the parallel sampling technique applied to its first stage is implemented in CMOS 65 nm technology. It achieves a full-scale input signal range of 2 V differentially with a 1.2 V supply voltage. Simulations show more than 5 dB improvement in signal-to-noise-and-clipping-distortion ratio (SNCDR) and around 8 dB improvement in dynamic range (DR) compared to a conventional 11b ADC for converting multi-carrier signals, simulations also show that is able to achieve a comparable SNCDR and noise power ratio (NPR) as a conventional 12b pipeline for converting multi-carrier signals with less than half the power and area