Add to ORKGScalable formal verification constitutes an important challenge for the design of complicated asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We propose to use Click, an existing library of asynchronous primitives, for verification. We present the automatic extraction of abstract SAT/SMT instances from circuits consisting of Click primitives. A theory is proven that opens the possibility of applying existing deadlock verification techniques for synchronous communication fabrics to asynchronous circuits
Abstract. We present a type-based deadlock-freedom verification for concurrent programs with non-blo...
AbstractFormal verification is increasingly important in asynchronous circuit design, since the lack...
[[abstract]]In this paper, we present a new compositional verification methodology for efficiently v...
Scalable formal verification constitutes an important challenge for the design of asynchronous circu...
Abstract It is important to verify the absence of deadlocks in asynchronous circuits. Much previous ...
This article investigates how the use of approximations can make the formal verification of concurre...
This paper illustrates the practical application of an automatic formal verification technique to ci...
International audienceAsynchronous circuits have key advantages in terms of low energy consumption, ...
This work develops a type of local analysis that can prove concurrent systems deadlock free. As oppo...
We present a type-based technique for the verification of deadlock-freedom in asynchronous concurren...
Communication fabries constitute an important challenge for the design and verification of multi-cor...
Abstract. We propose a modular verification technique that guarantees the absence of deadlocks in a ...
Abstract. This paper presents an expressive specification and verifica-tion framework for ensuring d...
Modern asynchronous digital circuits are highly concurrent systems composed largely of customized ga...
Part 3: VerificationInternational audienceFor a system-on-chip design which may be composed of multi...
Abstract. We present a type-based deadlock-freedom verification for concurrent programs with non-blo...
AbstractFormal verification is increasingly important in asynchronous circuit design, since the lack...
[[abstract]]In this paper, we present a new compositional verification methodology for efficiently v...
Scalable formal verification constitutes an important challenge for the design of asynchronous circu...
Abstract It is important to verify the absence of deadlocks in asynchronous circuits. Much previous ...
This article investigates how the use of approximations can make the formal verification of concurre...
This paper illustrates the practical application of an automatic formal verification technique to ci...
International audienceAsynchronous circuits have key advantages in terms of low energy consumption, ...
This work develops a type of local analysis that can prove concurrent systems deadlock free. As oppo...
We present a type-based technique for the verification of deadlock-freedom in asynchronous concurren...
Communication fabries constitute an important challenge for the design and verification of multi-cor...
Abstract. We propose a modular verification technique that guarantees the absence of deadlocks in a ...
Abstract. This paper presents an expressive specification and verifica-tion framework for ensuring d...
Modern asynchronous digital circuits are highly concurrent systems composed largely of customized ga...
Part 3: VerificationInternational audienceFor a system-on-chip design which may be composed of multi...
Abstract. We present a type-based deadlock-freedom verification for concurrent programs with non-blo...
AbstractFormal verification is increasingly important in asynchronous circuit design, since the lack...
[[abstract]]In this paper, we present a new compositional verification methodology for efficiently v...