Smart and flexible DACs, classification and design

This paper classifies correction methods for current-steering Digital-to-Analog Converters (DACs), with an emphasis on self-calibration. Based on this classification, missing methods are identified. Three new DAC correction methods are proposed that can fill in these gaps: high-level mapping, suppression of HD, and calibration of binary currents. All three of them are based on parallel sub-DACs. The paper also proposes to further exploit the advantages of using such parallel sub-DACs to achieve flexibility. Two test-chip implementations in 250nm and 180nm CMOS validate the proposed concepts