Development of alternative pulse width modulation methods for conventional and multilevel voltage source inverters

This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University LondonMultilevel inverters have attracted wide interest in both the academic community and the industry for the past decades. Therefore, the investigation and development of modulation strategies in multilevel inverters emerges as a necessity for the industry and researchers. In this doctoral thesis, alternative modulation methods suitable for three-level conventional single-phase inverters and especially for cascade H-bridge multilevel inverters are discussed and proposed. The theory of Equal Areas is reformed and presented and its modifications are proposed. These modifications are compared with other well-known modulation schemes, such as carrier-based modulation schemes and programmed pulse width modulation techniques. The advantage of the modified Equal Areas Pulse Width Modulation (EAPWM) is its algorithmic simplicity due to simple algebraic relationships, which results in less computational effort. A fully mathematical formulation for the Equal Areas modulation is proposed for both conventional and multilevel inverters. The EAPWM is shown to produce well-formed switched output voltages that have low total harmonic distortion at even low switching frequencies. The importance of this thesis is complimented by the results, produced after the implementation of EAPWM in multilevel inverters, which can be used as a more accurate reference when compared with other modulation strategies. Moreover, this direct modulation strategy has been extended to work on higher amplitude modulation ratios, in a linear manner, while entering the over modulation region. In this context, modified algorithms have been developed using different criteria for the calculation of the pulses’ width and their placement inside the time interval. The equal areas method, implemented in conventional single-phase inverters, uses odd pulse numbers per half cycle, holding integer frequency ratios in contrast to its implementation in multilevel inverters, where non-integer frequency ratios occur due to the level-by-level application. The application of the method is verified by simulations together with experimental work using a full-scale prototype inverter