APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description

Design of array processors needs suited CAD tools for each design phase, from behavioral description to physical layout. In this paper we present the main characteristics and the implementation details of an experimental environment for behavioral definition of array architectures: in particulars we consider textual and graphic data entries to increase the flexibility of the system and the interactivity with the user. To verify the correctness of the design, a simulator of the behavioral description was implemented: translation of textual and graphic definitions into an executable format, suited for simulation, is also discussed