Fabrication and Characterization of Silicon Nanowires with Width Down to 1.9 nm

Electron beam lithography, low-damage dry etch and thermal oxidation have been used to pattern Si nanowire devices for sensing applications with physical Si widths down to 1.9 nm. The electrical properties as a function of wire width and doping density have been studied and start to demonstrate depletion effects for devices with lithographic widths below 20 nm for wires doped at 8x1019 cm–3 and 30 nm for wires doped at 2x1019 cm–3. Si nanowires are being investigated for applications including transistors, sensors, electrometers and thermoelectric generators. Whilst many examples of bottom-up nanowires have been demonstrated, top-down fabrication techniques still dominate manufactured devices. This paper describes the techniques to fabricate Si nanowires down to 1.9 nm widths and the electrical and physical properties of the fabricated devices