(Invited) Technology options to reduce contact resistance in Nanoscale III-V MOSFETs

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (Rext) be minimized. Among the different components of Rext, contact resistance (RC), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower RC. However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these RC reduction options and present some of our recent results on contact/junction engineering to lower RC in III-V MOSFETs