Analysis and modeling of high performance and low power UTB SGOI devices scalable to Sub 30 nm

An evaluation of the Silicon- Germanium on Insulator (SGOI) MOSFETS is reported by implementing a 2D device design flow using a commercial Technology CAD (TCAD) tool within the context of optimizing the device design for high performance and low Power devices. The simulation is performed to develop SGOI based Ultra thin Body (UTB) MOSFETs. Device Simulations were performed for various Gate lengths, Body thicknesses, Anti punch doping and Si cap layer doping. It was found that, for a given body thickness and gate length, increasing the Silicon cap doping and anti-punch doping, the transconductance remains unchanged while Ioff, Drain Induced Barrier lowering (DIBL), Subthreshold slope and threshold voltages show improvement. Also, the devices with gate lengths 45nm, 32nm and 22nm demonstrate very good performance such as low leakage currents and good on current that are comparable to ITRS and hence can be implemented for sub-30 nm gate length devices