Module generators from topological descriptions and graph theoretic approach.

Because of the increasing complexity of the designs, there is a great necessity for automatic layout tools which produce results similar in optimality to those produced by manual design methods. The continuous progress in VLSI technology presents new challenges in developing efficient algorithms for the layout of logic cells. The feasibility of developing an automatic mask layout generator for switching trees from its symbolic counterpart is explored in this thesis. The symbolic layout is generated from a Switching Tree Layout Synthesizer which is then translated to the mask shapes. Each element in the symbolic layout represents an instance in the mask layout. The mapping of symbolic to mask layout is not constrained to just one solution. Depending on the overall structure of the design, necessary steps such as changing the transistor orientation and contact position and layout compaction for a particular section, are performed to obtain optimized and efficient layout. Two switching tree layout styles, DMS and IMS, are presented here which are dependent on the height and the width of the logic cell. A one-dimensional functional cell generator is also proposed in this thesis. Two algorithms to minimize the height and the width of the functional cell are studied and implemented based on graph theory. It is shown that the switching tree layouts are much more area efficient than that of one dimensional functional cells. Other advantages of the switching tree over other layout methods are also mentioned. Simulations are carried out to justify the heavily pipelining capacity of the switching trees.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1994 .S547. Source: Masters Abstracts International, Volume: 34-02, page: 0837. Adviser: Graham A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1994