On implementing the arithmetic Fourier transform (AFT).

This work investigates the VLSI implementation of the Arithmetic Fourier Transform (AFT) algorithm. The study proposes several different new architectures suitable for VLSI implementation of the AFT in Digital Signal Processing (DSP) applications. As a verification tool, Extend$\sp{\rm TM}$ is used to simulate the hardware realization of these proposed architectures. The motivation for this work is the recent rediscovery of the algorithm, by Tufts and Sadasiv (1), which has the possibility of eliminating many of the multiplications usually associated with computing discrete Fourier coefficients. The AFT implementations are based on nearest neighbour and linear interpolation procedures.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1991 .B458. Source: Masters Abstracts International, Volume: 31-01, page: 0385. Thesis (M.A.Sc.)--University of Windsor (Canada), 1991