High-level clock construction for low power.

Our work concentrates on high-level optimization of the power of clock network, which is a relatively new area. Our work includes two parts: activity-sensitive clock design for low power and low power clock based on clock frequency reduction. In the activity-sensitive clock design, we introduce the term of node difference based on module activity information, and show its relationship with power consumption. Merging power is used to measure the power cost of merging two nodes. A binary clock tree is built based on the merging power between different modules to optimize the power consumption due to interconnections (i.e., clock gating signals and clock edges). We also develop a method to determine the gating signals with least transitions. After the clock tree is constructed, we apply a local optimization on gating signals to further reduce the power consumption. In the clock frequency reduction, we propose a high-level power optimization scheme with two techniques: operator chaining, multiple clocks. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2002 .K36. Source: Masters Abstracts International, Volume: 41-04, page: 1153. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2002